Ashling Vitra-XS Debug & Trace Probe
Vitra-XS is Ashling’s Debug & Trace Probe for embedded development with support for multiple target architectures including RISC-V, Arm and Synopsys ARC powered systems. Vitra-XS works with Ashling’s RiscFree™ SDK for advanced embedded system debugging, tracing, profiling & analysis
Vitra-XS supports:
- Capturing & viewing of program-flow & data-accesses trace in real-time, non-intrusively
- Program downloading from the host PC to the target embedded system
- Exercising program in the target (go, step, halt, breakpoints, interrogate memory, registers & variables etc.)
- Fast, trouble-free “plug-&-play” installation using SuperSpeed USB3.0
- Supports RISC-V debug & trace standards including E-Trace & N-Trace (including SiFive Insight Trace and Debug IP)
- Supports Arm CoreSight™ debug & trace standards including SWD, DAP, ETM, PTM, STM & CTI
- Supports Synopsys ARC Real-Time Trace (RTTv2 or greater with 8-bit or dual 8-bit ports)
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Vitra-XS for ARC Debug & Trace Probe
Vitra-XS is a Debug & Trace Probe for embedded development with support for Synopsys’ ARC & ARC-V Processors and is integrated into the Synopsys MetaWare Development Toolkit (MWDT).
Real-time trace provides some key advantages when it comes to debugging and validating embedded systems and by using trace, developers can easily see how execution arrived at a certain point, via a back-trace or instruction history, and can answer questions like “How did I end up in this function?” and “Why did my code crash?” Trace information can be captured non-intrusively meaning that the application’s real-time performance is not affected and allows developers to profile their code to find out where time is actually being spent and to determine if performance related timing requirements are being met.
Vitra-XS for Arm Debug & Trace Probe
Vitra-XS is Ashling’s Debug & Trace Probe for embedded development with support for multiple target architectures including Arm, RISC-V and Synopsys ARC powered systems.Vitra-XS works with Ashling’s RiscFree ™ SDK for advanced embedded system debugging, tracing, profiling & analysis.
Vitra-XS supports:
- Capturing & viewing of program-flow & data-accesses trace in real-time, non-intrusively
- Program downloading from the host PC to the target embedded system
- Exercising program in the target (go, step, halt, breakpoints, interrogate memory, registers & variables etc.)
- Fast, trouble-free “plug-&-play” installation using SuperSpeed USB3.0
- Supports Arm CoreSight™ debug & trace standards including SWD, DAP, ETM, PTM, STM & CTI
Vitra-XS for RISC-V Debug & Trace Probe
Ashling is a member of RISC-V International working closely on the evolution of RISC-V and we are a leading supplier of RISC-V development tools including our RiscFree™ SDK, Opella-XD Debug and Vitra-XS Debug & Trace Probes which are described below. Ashling also engages and cooperates with leading OEMs and semiconductor companies to successfully develop custom RISC-V engineering solutions including Tools and Services. The combination of Ashling’s deep technical know-how and a close working relationship with the end-customer enables us to provide best-in-class solutions tailored to your needs.
RiscFree™ is Ashling’s Integrated Development Environment (IDE) and Debugger for RISC-V based development.
Features include:
- IDE based on Eclipse with full source and project creation, editing, build and debug support.
- Integrated GCC and/or LLVM compiler toolchains.
- Full support for all RISC-V 32-bit and 64-bit cores including:
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- Alibaba XuanTie C906, C910, E902 & E906
- Andes:
32-bit: N25F, D25F, A25, A25MP, A27, A27L2, N45, D45, A45 & A45MP
64-bit: NX25F, AX25, AX25MP, AX27, AX27L2, NX45, AX45 & AX45MP - CAES (Cobham-Gaisler) NOEL-V
- CAST BA51 and BA53
- CHIPS Alliance SweRV
- Codasip L11, L31, A70 and A730 processors
- Efinix Sapphire
- Gigadevice GD32V
- Imagination Catapult family including the RTXM-2200
- InCore RISC-V Azurite and Calcite Cores
- Intel Nios V
- lowRISC
- Lattice Semiconductor RISC-VMC CPU soft IP
- MachineWare SIM-V RISC-V ISS
- Microchip Polar RISC-V SoC FPGAs
- MIPS eVocore P8700 & eVocore I8500
- NXP
- Open-ISA VEGA
- OpenHW Group CORE-V-MCU
- PULP Platform
- Rocket
- SiFive:
32-bit: E2, E3 and E7 series
64-bit: S2, S5, S7, U5 and U7 series - Synopsys ARC-V RMX, ARC-V RHX and ARC-V RPX families
- Syntacore
- VexRiscv
- WD SweRV EH1, EH2, EHX3 and EL2 series
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- Heterogeneous (e.g. Arm + RISC-V) and homogeneous debug support for multi-core SoCs sharing a single debug interface (e.g. via JTAG, cJTAG or Serial Wire Debug (SWD)).
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